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A Device Matching Method For CMOS Analog Integrated Circuit Layout Design

A Device Matching Method For CMOS Analog Integrated Circuit Layout Design

Jan 17, 2018

Due to the uncertainties and random errors or gradient errors, some of the tubes which are exactly the same in theory and actually are deviant are produced in the process of integrated circuit processing. This deviation is called device mismatch. The characteristics of analog circuits are greatly influenced by the mismatch characteristics. The accurate description of the analog circuits is of great significance to the design of analog circuits. With the continuous development of semiconductor technology and the shrinking of processing dimension, the distribution of device structure and electrical parameters caused by the distribution of process parameters directly causes device mismatch and yield reduction. Therefore, the component mismatch caused by the distribution of process parameters is a factor that must be considered in the layout design process. This paper introduces the design rules of device matching for layout design of analog circuits, and focuses on the skills and methods of matching elements, such as transistors, resistors and capacitors, in analog circuit layout design.


1.  Design method of basic device layout matching

The CMOS analog circuit mainly produces some very precise voltage and current signals. In these analog circuits, there are some high voltage and large current signals. The influence of some noise sources on some sensitive signals is the key of circuit design. At the same time, some analog circuits have been developing in the direction of low voltage, small current and high speed after entering the deep submicron process. Therefore, how to draw the exact layout to match the simulation of the analog circuit becomes very important. In this paper, the basic matching mode of tube, MOS tube, resistance and capacitance in the design of analog circuit layout will be mainly introduced.


1.1  Device layout matching

Matching rules can help layout engineers to achieve accurate width and length of transistors in analog circuits, and accurate resistance and capacitance values, so that the chip of analog circuits has a very good function.


1.1.1  Matching rule

The matching rules of the shape and direction of the analog circuit layout are the same, and the layout of some sensitive devices should also follow the rules of the layout matching. Generally, the design techniques of component matching should be considered in the following aspects:

(1)Element size: the irregularity of the small size device leads to the deviation of the device. Increasing the size can increase the matching percentage between the two matching elements. But when the size is too large, it will increase some parasitic effects, such as parasitic capacitance.

(2)Direction: the difference of transverse process (diffusion gradient, temperature gradient, mask alignment deviation, etc.) will cause the matching of the device. When the component is close and the direction is consistent, the mismatch caused by the transverse process error can be reduced. The best matching elements should have the same shape, the same size, tight cluster and the same direction.

(3)Temperature: the existence of power dissipation elements on chips will cause mismatch of components, because the power dissipation of large resistors or large size devices will cause temperature gradients on the chip. For example, the junction temperature of a high-power device will be a few degrees higher than that of other devices, and the reverse saturation current of the bipolar transistor is greatly dependent on the temperature. Therefore, the devices that require matching in the layout design should be equal to the heat source, especially for the key components in the circuit, such as the differential discharge tube.

(4)Contact hole position: sometimes a contact hole position of the device will match the bad, as shown in the figure, the resistance is saddle shaped, when the contact hole deviation due to process level moves, a resistance increase, while another resistance decreases, resulting in a two resistor matching variable the difference in the design, to avoid using this form of resistance.

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(5)Metal wire: considering the reflection and diffraction of light, in order to reduce the deviation of the intermediate process, the situation around the key figures should be roughly equal, so as to avoid the size of the key graphics affected by exposure.


For example, in the transistor requires high matching accuracy to avoid let metal wires through the active gate region; lead through the transistor matching accuracy is not high, but the need to add a (virtual) wire, so that the wire of the same length along the channel from the same location in each matching array part.