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A New Method For Layout Verif Icat Ion Of Integrated Circuits

A New Method For Layout Verif Icat Ion Of Integrated Circuits

Jan 15, 2018

1.  LVS tools

LVS ( Layout Versus Schematic) is used to confirm the consistency of the layout and the schematic. LVS compares the correctness of the layout and schematic connection at the transistor level, and lists the differences in the form of the report. Dracula generates layout data from a graphical system. Dracula converts the GDS2 format layout file to the layout net table, and LOGLVS ( The Dracula Netw o rk Compiler ) transforms the gate and transistor level net tables described by Schematic or CDL to the LVS net table. Starting from the input and output of the circuit, a progressive search is carried out to find a nearest return path. When LVS finds a matching point, it gives a matching state to the matched device and node; when the LVS finds a non matching point, it stops the search of the path. After LVS searches all the paths, all the devices and nodes are given a matching state. Through these States, the matching of the circuit and the layout can be counted. The operation flow of LVS is shown in Figure 1.

1.png

1.2 unit structure type

The circuits extracted from the layout and the original design of the network must be transformed into the same form of net table structure, and the same structure unit is interconnected, and the two are comparable. In order to reduce the workload of comparison, some of the low level device for gate level combinational circuit, including the structure of MOS unit circuit: INV (inverter), NOR (two input "or not"), NAND (two input NAND gate, two input (AOI) "and or not" OAI (two), input "or NAND gate"), PUP (parallel pull (connected power supply)), PUPI (inner parallel pull), SUP (Series pull (on power)), SUPI (inner series pull), PDW (parallel drop-down (under the ground)). PDWI (inner parallel down), SDW (drop (under ground) series, SDWI (inner), PMID series (down) parallel middle (parallel transmission gate), SMID (middle) series (serial transmission gate)). The number of these structures can be seen in the report. Mismatches include the sum of gate and transistor level devices. Devices that can not be assembled into units appear in the form of the most basic structural unit MOS devices.


1.3 LVS error types

The error types of LVS are generally divided into two types: inconsistent points and mismatched devices. The inconsistencies can be divided into node inconsistencies and device inconsistencies. The node disagreement means that there is a node in the layout and the circuit, and the two nodes are similar, but not exactly the same. The disagreement of the devices means that there is one device in the layout and the circuit, the two devices are the same, and the nodes connected are very similar, but not exactly the same. A mismatched device refers to some of the devices in the schematic diagram that are not in the layout, or in the layout, but not in the schematic diagram. Specifically, there are fifteen types of errors in LVS:

There are fifteen types of error in LVS:

1. There is no device on the matched node.

2. matched devices have mismatched nodes.

3. devices do not match;

4. matching nodes have redundant layout devices.

5. matching nodes have redundant circuit diagram devices.

6. matching nodes have unmatched layout and circuit diagram devices.

7. other mismatched layout devices;

8. other mismatched circuit diagram devices;

9. The type of device (type N and P, polycrystal resistance or diffusion resistance) is not matched;

10. The size of the device (W or L) does not match.

11. MOS reversibility error;

12. substrate connection is not matched;

13.The power connection of the device is not matched (the situation of multi power supply);

14. simplifying multiple and connecting MOS to a single MOS is an error (related to the K option in LVSCHK);

15. error when filtering redundant devices (related to the F option of the command in LVSCHK).


  A LVS error refers to a single device, a single node, and a composite structure (a sub circuit). A mismatched sub circuit (multiple devices and nodes in a sub circuit) is often one of which is not matched with several nodes or devices, and not all of them do not match. All devices and nodes associated with a mismatch are used as the number of errors, and each of the mismatches is listed in the LVS report file. Erroneous reports are different from people's usual understanding. For example, two signal lines are switched to locations. According to common sense, they can only be counted as a mistake, but there are two errors in the LVS report.