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Dealing With False Error In Hierarchical Design Rule Checking

Dealing With False Error In Hierarchical Design Rule Checking

Mar 01, 2018

 With the expansion of the scale of integrated circuits (IC), the hierarchical design method has become the mainstream of IC design. Because the scatter layout verification tool processes data from the entire layout to the chip level, verification for the modern IC layout often takes dozens of hours, and often cannot be completed because of insufficient memory. In this way, a hierarchical layout verification method is proposed, which uses the hierarchical structure of the layout to verify the different units respectively. The hierarchical design rule checking (DRC) is an important tool in the hierarchical layout verification system. In modern VLSI layout, there are many units being called repeatedly, while hierarchical DRC checks all kinds of units only once. Therefore, hierarchical DRC will greatly reduce processing effort and shorten DRC running time. At the same time, because only one unit is handled only each time, the memory requirement is also significantly reduced.


 In addition, the classified DRC puts the errors found in the corresponding unit and facilitates the designer to modify it. Nevertheless, the hierarchical DRC algorithm presented in the literature now has more or less restrictions on layout. When dealing with it, there will be a series of special problems of hierarchical method. Among these problems, the problem of false and false appears to be particularly difficult. To solve this problem is of great significance to the practical application of graded DRC.


 The brief flow of the hierarchical DRC algorithm is: traversing the unit call tree in the back sequence and breaking the DRC graph set of each unchecked unit as a scatter DRC. The DRC graph set of a unit consists of the following elements: the graphic of the unit itself, the abstraction of each sub unit of the cell, the graph covered by the overlapping area of its sub cells, and the graph covered by the overlapping area of the unit graph and the sub cell. According to such a process, hierarchical DRC produces false errors, mainly because the graphic operation is inappropriate in the process of forming DRC graphical set, which changes the original shape of the graph, and the unit itself has incomplete graphics. In this paper, the corresponding solutions are put forward.


1 False error caused by improper graphic operation

1.1 Extraction unit abstraction

  In the IC layout, the cell and the outside world are usually only exposed to the boundary. Therefore, drawing the DRC within the unit scale is used as a unit abstraction to check whether the design rule is violated between the unit and the external graphics. The unit abstraction that is extracted directly from the peripheral ring of the cell (that is, logical AND operation), is able to satisfy the DRC check of its surrounding graphics when it is invoked. But because cutting will change the shape of the original figure, it may produce false errors when checking the abstract graphics. As shown in Figure 1 (a) shown in the unit, cutting unit are abstract as shown in Figure 1 (b) in the shadow, when the abstraction by other units call, as scattered DRC in a call unit, check the width of 2 of the original graphic graphics for was not wrong, but in Figure 1 (b) from being cut off a block will be wrong. The same reason, the check of the concave width of the figure 1 becomes a check of the interval of the same layer, and of course it is even more wrong.

1.png



  From where the graphic operation tools and scattered DRC tool does not recognize the pattern extraction unit case, abstract we must adopt a new way: as long as there is a drop in the graphic unit ring, the graphics of the fetching unit to maintain the original abstract graphics, figure 1 (c) is extracted in this way the unit of abstraction, which contains the complete graph 1 and graph 2, being raised will no longer cause false errors.


1.2  Drawing under the overlay

 If the cell has a graph in depth (or overlap), if its sub cell is overlapped, the inner graph of the sub cell may violate the design rule with the outside world, so we need to put forward the overlapping unit graph to check it. Due to the same reason, we should not change the shape of the original graph when the sub cell graph under the extraction unit graph is covered, and the sub unit graph covered by the overlapping area of the sub cell, otherwise, it will also produce false error.

2.png

  Figure 1 in Figure 2, figure A, goes deep into its sub unit B, the overlap between parts B and C, enlarging the overlap part of a DRC size, as shown in the dotted line of the graph, when drawing the graph under its cover, it should be the whole figure, rather than the part cut by the dashed line. Therefore, the graphics 2, 3, and C units of the complete B unit should be extracted and incorporated into the DRC graph set of its parent unit A.


2  False error caused by incomplete unit graphics

 For a variety of design considerations, may allow for incomplete graphic elements, such as a bus or half a hole on the unit alone as DRC will complain, but the unit was raised, by combining with other graphics, and no error. As shown in Figure 3. Obviously, this is a false mistake. The existence of such a situation brings great trouble to the hierarchical DRC processed by the unit. It forces the hierarchical DRC to consider the cell and its calling environment together.

3.png


In this regard, the following measures are put forward:

(1)The unit of error graph transformation to the chip level, remove the surrounding related graphics, again beaten DRC, due to faulty graphics and related graphics is very small compared with the number of scattered to the graphics chip level total, so the processing speed than DRC can. The final result is to get rid of the wrong results of DRC.

(2)In the chip, where the unit first appears, the unit is put into a set of DRC graphics originally used for a scatter check, and the later calls are abstracted. Break the whole layout of this layout for DRC, as shown in Figure 4. This is actually a variant of hierarchical DRC, which put all units in chip level to process, and excavate repetitive parts to reduce the workload of DRC. At the same time, it checks the surrounding environment of chip at chip level. This method is suitable for dealing with layout rules and regular overlaps.

(3)In the actual layout, due to incomplete graphics in almost all units around the unit in the unit and abstract abstract graphics, will be in the unit every time when calling the surrounding environment with inspection, therefore, can be made in flat check on each unit of DRC sets of figures, which do not involve the unit that is the unit of abstraction within the surrounding graphics of DRC will be raised in the unit, it can reduce the false error generated, but need graphics computing tools and DRC tools can scatter where pattern recognition from.

4.png


(b)Each unit in the chip level DRC graphics layout, such as the shadow part of the diagram, of which B-1, C-1, D-1 are the first appearance of B, C, D units.

Figure 4 a hierarchical DRC chip level graphic layout for a variety of varieties


  The above methods have their own limitations. If we combine the inverted layout tree method shown in Figure 5, we integrate (2) and (3) two ways, take account of various environmental factors of chips at chip level, and carry out hierarchical DRC, which can better solve the pseudo error problem. The inverted layout tree records the call relation of the unit at all levels, and can be used to find the calling environment of the unit. For example, for the layout layout of the figure 5 (a), the inverted layout tree of the unit D, such as 5 (b). It shows that unit D is called two times in B and 3 times in C. In chip A, cell D is directly called by A for 3 times, as a sub unit of B and C, and is indirectly called by A for 7 times. Therefore, at A level, 10 D units appear on the whole chip. In order to eliminate the false error caused by incomplete graphics, the unit should be taken into consideration in the chip level together with its environment. The use of hierarchical DRC can improve efficiency, mainly based on the multiple unit call environment in the hierarchical design layout. For example, although the unit D is called 10 times in the chip A, only two adjacent cases in the DRC check scale are adjacent to the D or adjacent to the E. Therefore, only these two conditions should be examined as the environment of the D.

5.png


(unit D is invoked as a subunit of B1 and B2. As a sub unit of C, C1, C2 and C3 are invoked; A8, A9, and B are called directly as A sub units, because they are indirectly invoked by calling and calling. )


  The error of the unit in various environments should be put into the error set of the unit, that is, the DRC error reported by each unit should be the result of the set intersection operation. The inverted tree is easy to put the wrong results in the most suitable units, so that the result of the classification is obtained so as to make it easy to modify. For example, in Figure 5 (b), D's errors in all the invocations at the chip level should be reported in D. Errors occurred only in A1, A2, A3 and A4 are reported in B unit. The error occurred only in A3 is reported in A unit.