The first step to use Dracula is also a key step, which is to create a command file (rules file) that is consistent with its layout technology, and extract the layout data through Dracula command file to form the layout network table. During the compilation process, if Dracula finds an error, the wrong type will be prompted, and the command file is debugged according to the information until it is completely passed. The Dracula layout validation process is shown in Figure 2.
The Dracula command file structure consists of the following four parts (each block begins with a "* block name", ends with "* END", and the behavior of the semicolon header is commented).
1) the description block: including the path and name of the input and output files, the top-level cell name to be detected, the CAD layout system name, the scale factor of the graphic unit and the execution mode.
In the IN DISK one, write the GDS file name out of the Stream out, and write the path if it is not running under the current path.
IN DISK= /home /cell — desig n /x x x. gds
2) input layer block: the GDS number in the layout corresponds to the layer number in the command file (the computer only identifies the GDS level number, and has nothing to do with the name of the specific layer). as
Otherwise, LVS can't run normally. The command files must be closely integrated with the process, and different command documents are required for different processes.
3) operation block: the main part of the command file. The extraction of the layout, combined with the specific process, the structure of the layout to identify the various components and connections in the map. By using logical topological relations between layers and And, Or, Not, Inside, Enclose and other commands, we establish recognition layer, device connection and device electrodes. The extraction of layout circuit is an important means of layout verification, which regenerates the circuit according to the layout information. In the Dracula tool operation block, the logical operation of the combination of the original layer, the prebuilt layer and the input layer is used to identify the components and the line forming network table. The following is the Pwell - CMOS process as an example.
Through the above command, the recognition layer is generated and the connection layer is specified.
； * * * CONN ECT LIST * * * *；
Finally, the NMOS tube and the PMOS tube can be identified by the description of the components.
In the operation of the block, we will be on chip technology and device structure are defined, the original in physics, not every edition associated extraction into various basic elements in the integrated circuit, and circuit principle diagram generation network expression to the same level of transistor, can become the object of comparison. Therefore, all the components used in the design of the circuit must be explained in the operation block.
In CMOS integrated circuits, the basic devices are NMOS, PMOS, MOS capacitors, polysilicon resistors, various diffusion resistors and diodes. In BiCMOS integrated circuits, there are also NPN and PNP. Taking the simplest MOS tube as an example, polysilicon can be used as "and" of the N+ or P+ diffusion zone, which is defined as a NMOS or PMOS tube. However, not all devices have such clear structural features, and some devices have a slightly different definition. The following is a detailed analysis of the polysilicon resistance as an example. In the design of the chip, polysilicon can also be used as a connection except for metal. Therefore, we must include polysilicon when we define the connecting layer. In fact, there is no difference between polysilicon connection and polysilicon resistor in process realization. Physically, they are all the same. They only use different physical properties of polysilicon to achieve different functions. In this way, the polysilicon resistance can not be extracted directly from the layout. The solution is to artificially add a level, drawing on the location of the polysilicon resistance on the layout, to be different from the general polysilicon line. When the LVS file is written, the polysilicon resistance can be obtained by using the polysilicon and the added phase "and". The method of extracting the polysilicon resistance is also applicable to various other devices, including various diffusion resistors, diodes and triode.
For the non ordinary CMOS and BiCMOS processes, there will be some special devices in the circuit. For example, in many high voltage integrated circuit chips, there will be a new type of power device such as LDMOS, which is integrated inside the chip. The structure of these special devices is very complex, it is very complex and time-consuming to use the precise definition of the statement, and these devices can be explained by a method similar to the detection of the polysilicon resistance. Because the number of such devices is very small, it can be separated by an additional layer. The device can be defined in detail, and with manual inspection, the purpose of inspection can be achieved. The LVS inspection is mainly to ensure the correctness of the connection between these devices and other devices. The following is a detailed introduction to the LDMOS devices in the high voltage integrated circuit chip.
LDMOS is a transverse short channel multichannel device which is widely used in high voltage and low current fields in high voltage integrated circuits. As shown in Figure 3 and Figure 4, compared with the CMOS of the pass, a high resistance layer called drift region is designed between the source area and the leakage area of LDMOS, in order to improve its withstand voltage capability. The complex structure of high voltage devices mainly refers to the complexity of the process. But from the point of view of the extraction, the Dracula language needs the topology of the layout, and the operation can be separated from the process. Therefore, in the process of compiling the LVS command file, we only need to process the graphic structure of LDMOS. We use Dracula language to identify components and integrate netting with netting. The LDMOS tube is extracted by the following program.
4) the drawing block (optional): send the output file to the device such as the plotter. Command file is directly related to check the accuracy of height, omission, misstatement, false all affect the design of the first successful rate and time to market.