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Full-Custom Layout Design Based On The Platformof Zeni EDA System

Full-Custom Layout Design Based On The Platformof Zeni EDA System

Jan 04, 2018

 1. Basic concepts

1.1  Territory

The layout is the design process of transforming three-dimensional solid structure into two-dimensional geometric figure. It is a set of mutually integrated graphics, with different layout corresponding to different process steps, and each layer is represented by different patterns. It includes the related physical information of the circuit size, the topology of each layer and other devices. It is the final output that the designer delivers to the plant.


1.2  Layout design

It converts every component, including transistors, resistors, capacitors and so on, into the layout information needed for integrated circuit manufacturing. It mainly includes the steps of graphic division, layout planning, layout and wiring, and compression. Layout design is a necessary step to achieve integrated circuit manufacturing. It is not only related to the function of integrated circuit, but also affects the performance, area cost, power consumption and reliability of integrated circuit to a certain extent. Layout design is the bridge of integrated circuit from design to manufacturing.


1.3  Implementation of integrated circuit layout

The implementation of integrated circuit layout can be divided into full customization (Full- Custom) design and semi customization (Semi- Custom) design. Semi custom design includes gate array design, door and sea design, standard cell design, block design and programmable logic device design. The whole custom design method is based on the human-machine interaction graphic system, which is designed by the layout designer from the graphics and dimensions of every semiconductor device until the layout and routing of the entire layout. The characteristics of the full custom design is to optimize the circuit parameters and layout parameters for each component, and get the best performance and the smallest chip size, which is conducive to improving the integration and reducing the production cost. With the continuous progress of design automation, full custom design

The proportion is declining year by year.



2.  A brief introduction to the nine day EDA system

Application of Huada electronic extension nine days EDA system is a large-scale integrated circuit design EDA tools developed by China and is compatible with the international mainstream EDA system, integrated circuit design scale to support millions of gates, can be the standard international general data format conversion, it has been applied in the more than 20 colleges and universities in commercial Integrated Circuit Design Company and Southeast University in China, especially play a role in the design and Simulation of high speed integrated circuit, successfully developed a number of practical integrated circuit chip. It mainly includes the following several parts: ZeniSE (Schematic Editor) principle diagram editing tool, it can be EDIF format conversion, Spice embedded simulation support for third party); ZeniPDT (Physical Design Tool) the layout editor; it can provide multi window multi unit layout editing function, and can support millions of gate size the map Editor (Physical Design Verification ZeniVERI; Tools) layout verification tool which can be used in geometric design rule checking (DRC) electrical rule check (ERC) and logic netlist and layout netlist comparison (LVS) such as layout design tools module is ZeniPDT, it has a hierarchical design rule checking and online editing ability the design process, and provides the interface as shown in Figure 1 to write standard data,

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3.  Design examples

Any one of the CMOS digital circuit system is composed of some basic logic unit (not, NAND gate, nor gate), and the basic design of cell layout is based on transistor level circuit design. In layout design, it involves how to design the shape of the mask, how to arrange the location of the transistor, the location of the contact hole, and the location of the signal lead. The following is designed for an example of a D trigger for data acquisition.


3.1   Circuit diagram and working principle of D flip-flop

D trigger circuit, as shown in Figure 2, this circuit diagram is constructed through ZSE module nine days EDA system tools, the basic working principle is: the first set CLB=1 when the clock signal CLK=0, DATA signals into the main register unit by conducting TG1, from the register due to TG4 conduction and the formation of closed loop, latch the original signal, the output signal from the CLK to maintain constant when the 0 jump to 1, the main register unit due to TG2 conduction and form a closed loop DATA signal latch for half the input signal, this also by TG3 via a NAND gate and an inverter output reached Q. When the CLK changes from 1 to 0, the D flip-flop enters the input signal and locks the original output state. The memory unit sometimes has to be set, and the CLB signal in the circuit acts as a trigger for 0 of the task. When CLB=0, the output of two was forced to 1 NAND gate in 0 or 1, regardless of the clock, the output terminal of the Q is set to 0.


3.2  Design of the layout of the sub unit of the D trigger

The D trigger is shown in Figure 2 consists of five inverters, two NAND gate, two transmission gate and two clock controlled inverters. Select the appropriate logic gate unit layout, and use these modules to form the D trigger.

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For the fully customized IC layout design, we need work platforms, including hardware design, EDA software design and process documents and rules files for layout design. The design hardware of this D flip-flop is a SUN Ultra10 workstation, the design software is nine days EDA system, and the 0.6um silicon grid CMOS process is used.


The CMOS inverter is the most basic unit in the digital circuit, which is composed of a pair of complementary MOS tubes. The above is the PMOS tube (load tube), and the following is the NMOS tube (drive tube). The logic functions of the inverter circuit can expand basic logic circuits such as "no", "no" and so on, and then get all kinds of combinational logic circuits and sequential logic circuits.


In a circuit diagram, the line drawn between the endpoints of each device is represented by a simple intersection of two lines. But for the specific layout of the physical layout, we must be concerned about the physical interrelationships among different interconnect layers. In the silicon CMOS process, the N type and the P type diffusion zone can not be directly connected.

Therefore, there must be a method of connecting the simple leakage between the physical structure and the physical structure. For example, at least one connection and two contact holes are needed in the physical layout. The wire is usually made of metal lines. The local symbol circuit layout of the inverter as shown in Figure 3 (a) can be obtained. Similarly, we can connect the source of MOS tube to the simple connection between power VDD and ground VSS through metal wire and contact hole. As shown in Figure 3 (b), the power line and ground wire usually use metal wire, and the grid connection can be made by simple polysilicon strip. Figure 3 (c) shows the inverse of the final symbol circuit layout drawn by the nine - day layout design tool as shown in Figure 4. The layout of other basic units can be established by this.

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3.3  Layout design of D flip-flop

First, a library named DFF is built, and each unit layout is stored in the DFF library, and a new unit named DFF is set up in the library. The subunits are called and the layout of the corresponding D trigger is arranged, followed by the connection between the units. The 1 layer is mainly used in metal, metal 2 and polysilicon wiring contact hole is used to connect the active region and the 1 metal, through holes to connect the metal 1 and metal 2, between polysilicon and polysilicon and the same metal layer connected directly after the completion of layout design, and then use the layout verification tool ZeniVERI layout design layout verification finally, after verification of D trigger layout as shown in figure 5.

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