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Layout Design For CMOS Analog Circuit

Layout Design For CMOS Analog Circuit

Jan 20, 2018

 The realization of modern CMOS technology system is more and more complicated, work faster and faster, and the working voltage is more and more low while reducing the device size saves chip area, reduce power consumption, improve the intrinsic speed, but different module the crosstalk and layout design of the non ideal, severely limits the system's speed and accuracy, so the layout design is an important aspect of analog circuit design of analog circuit unit, there are two principles: to minimize the chip area and will affect the parasitic components on the circuit performance fell to the lowest in this paper mainly introduces analog transistors and symmetry interdigital circuit layout. A brief description of resistor and capacitor layout implementation, and realize the interconnection.


1  CMOS unit circuit using folding method

  There are parasitic resistance and capacitance in the actual MOS circuit. This kind of parasitic parameter is mainly determined by the shape of the gate. Because the area of gate is determined by the design of circuit, it is impossible to set up the layout unit to reduce the gate capacitance of the device, but we can reduce some other parasitic capacitance by adjusting the set shape of the device, such as PN junction capacitance. For analog integrated circuits, because of the great influence of the size of the node capacitance dynamic performance of the circuit, the parallel transistor structure, MOS tube in the same width length ratio, adopts a structure of common source and drain region, greatly reduced the total area of source and drain regions, thus decreasing the node capacitance at the same time. Reduced MOS device source and drain PN junction capacitance pole, to improve the dynamic characteristics of the circuit.

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 According to experience, using a folded gate MOS tube, the width of each finger transistor should be selected to ensure that the gate resistance of the transistor is less than the reciprocal of its transconductance. In low noise applications, the gate resistance should be 1 /gm, 1 /5 to 1 /10, and the number of parallel MOS tubes is also the number of interdigits, which is determined by the channel width W of the device and the channel width of the small size MOS pipe corresponding to each interdigital. In addition to considering the performance optimization of single device, the aspect ratio of small size MOS tube must also consider the area occupied by all parallel devices, the layout requirements of layout and the influence of process dispersion.


 When interdigital structure is adopted, the different fork index has different influence on the performance of the circuit. The following 3 interdigitated fingers and 4 interdigitated device structures are taken as examples to illustrate the similarities and differences between odd and even interdigits. As shown in Figure 2.

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 The odd numbered device structure is equal in the area of the source leakage area, that is, the same source capacitance and the drain capacitor. For the device structure of even numbered finger, the number of source leakage regions is not equal, and the difference between the two is an active region. Therefore, the total area of the source and drain is different, so the corresponding capacitance is also different. When designing the layout, we must consider which pole is sensitive to the capacitance, and then reduce the area of the corresponding pole. The smaller the area, the smaller the capacitance.


  From the above analysis, in the design of interdigital transistor, should as far as possible the use of odd interdigital method is adopted to a transistor into a plurality of parallel finger transistor, although has the advantages of reducing gate resistance, but significantly increases the capacitance around the source and drain region. For odd numbers of folding (the fork index is N), the circumjacent capacitance of the source drain area:

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   E is the length of the leakage area, the W is the width variable, and the Cjsw is the side wall capacitance of the unit length.


 It is found from the upper form: if the W of the MOS tube is certain, to reduce the capacitance Cp around the source leakage area, the N and E must be far less than the W value. But in practice, sometimes this principle will be in contradiction with the reduction of gate noise ratio, and the corresponding method should be adopted according to the practical application.


2  Error and mismatch of MOS tube

 The electrical properties of the identical devices are not exactly the same after the completion of the process and material properties and parasitic effects. Therefore, the individual devices and layout design, the device must be fully taken into account the mismatch and error problem, through the layout design to avoid or reduce the mismatch error and figure 3 (a) in the differential pair as an example, figure 3 (b) two MOS with different direction of the tube, easy by ion implantation the anisotropic geometric distortion caused by mismatch. The layout shown in Figure 3 (d) is a common source structure. When there is shadow generated by the injection angle, one is located in the drain area and the other is located in the source area, which makes the two MOS tubes mismatch. Figure 3 (c) is a good symmetry.

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  In the actual layout, a virtual tube is usually added to both sides with figure 3 (d) to enhance the symmetry as shown in Figure 4.

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 It is important in the direction of the line in the CMOS circuit simulation, as shown in Figure 5 (a) shows, there is a free metal line through the M1 side, which will reduce the symmetry, causing a greater mismatch between M1 and M2, in order to reduce the influence of the environment, be next to the M2 symmetry place a same wire (or suspended), as shown in Figure 5 (b) in order to avoid the mismatch effect of MOS pipe in the same direction, as shown in Figure 6, can take the cross complementary principle, each MOS tube and MOS tube into an even number, then cross placed, the realization of "concentric layout". This enables a match between M1 and M2. But considering the lead factor, wiring will be more complex, and the difficulty of wiring symmetry will be greater. Therefore, only in the input port of high precision operational amplifier will this form be adopted.

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3   Resistance matching and capacitance matching

  The matching degree of the polycrystalline resistance is a function of the geometric size. Most of the rules for the layout of the MOS device are also applicable to the resistance. The resistance of long and wide proportions strictly defined must be made up of the same unit resistance in series or in parallel (with the same direction). When designing a structure with proportional resistance, the electrical characteristics of the circuit are mainly related to the proportional accuracy, but it has a weak function relationship with the absolute value accuracy of a single resistor. In layout design, these proportional resistors often use the matrix connection structure to reduce the proportion error.


  For high precision circuits, the layout of the capacitor must follow the above principles for transistors and resistors. The error of capacitance mainly comes from the error of the area and the thickness of the dielectric layer. So it is similar to the proportional resistance. When each small capacitance is produced by the process error, the proportion of the capacitance can remain unchanged.


4  Wiring design of eliminating coupling

The capacitance between the signal lines can form a coupling effect. The following two cases have the formation of capacitance:

(1) the two signal lines overlap in different layers to form overlapping capacitors.

(2) the two signal lines are parallel to the same layer, forming a parallel capacitance.

It is possible to reduce overlap capacitance and parallel capacitance by reducing the overlap area and parallel length between conductors, and to connect a conductor with grounded or fixed potential between two parallel conductors to shield the crosstalk between them.


  The resistance effect of the power line also causes coupling, making the voltage unstable and forming the noise, and the power line can be shortened or widened to reduce the resistance.