1. Proper unit matching
The unit configuration usually refers to the placement and direction of the gate and the transistor level elements. It includes the determination of the specific shape of the unit and the selection of the azimuth of the unit. For MOSIC, it is meaningless to evaluate the performance of a single unit independently. We must analyze whether the configuration of each cell is suitable from the whole point of view, so as to reduce the actual occupied area of each circuit. The production practice shows that when the chip area is reduced by 10%, each big round piece is on the wafer.
The core product rate can be increased by 15%~20%. In order to reduce the chip area, should be used in parallel or gate circuit, less series circuit NAND gate form. In the graphic structure, the comb or horseshoe shape of the large span conduit is better, the area of the chip is small, and the strip pattern should be used for the small span catheter. For a load tube used as a large resistor, the length and width of the channel can be appropriately relaxed.
2. The wiring should be appropriate
The wiring is based on the connection of the circuit to connect the units and the corresponding welding points with the wires. With the improvement of integration, the wiring inside the chip is more and more complex. The total area occupied by the circuit is usually several times the total area of the chip. Therefore, the RC time constant of the wiring will be the main limiting factor of the circuit's working speed. In the silicon gate MOSIC, the main wiring is the metal wire and the polycrystalline silicon line, so it is often used as a type of wire.
Wiring in a horizontal direction and wiring in the other as a vertical direction. Figure 3 is a sketch of the MOS circuit wiring. Long distance wires, polysilicon and diffusion regions are generally used only for short distance connections. In order to reduce the parasitic capacitance, the length of polysilicon under the metal film is as short as possible when the polysilicon passes through the wire. To reduce the length of the wiring, especially to reduce the length of the wire, is an important sign of the suitability of the wiring. For those wiring to prevent crosstalk from each other, be sure to keep away from walking, and not to be reliable and parallel.
Power line and ground line is the two involving almost the entire global position each chip lead, their electrical properties and security routing results will have a direct impact on the chip, usually made of metal wire, metal silicide film used in deep submicron technology, VLSI layout design in power line design is very important, they are the lead the most complex wiring in. Because the current of the whole chip is to flow through the lead wire of the power supply wire, if the metal is introduced.
Line design too wide, will occupy a large area of the chip, if the metal wire is too narrow, the voltage drop increases lead resistance so as to affect the normal work of the circuit, electromigration rates can lead to premature failure of power supply wire; while others lead them with the same chip, a transistor to the local layout they, in the input protection circuit and the output pads around the driving circuit also need them. It is usually required that the width of the ground wire of the power supply is far greater than the width of the signal line. In order to meet the electrical performance requirements, the power supply and ground wire network must be placed on the same metal layer as much as possible. The wiring on the single-layer metal layer must meet the requirement that there is no cross plane requirement.
Figure 4 gives a network chip wiring of the power line and the ground wire.
3. IC layout verification
IC layout editor usually uses hierarchical design, at all levels, it is generally required to verify the layout, first simple and later complex, first low layer and then high level. IC layout validation includes:
1. geometric size rule check (DRC);
2. electrical rules inspection (ERC);
3. Extraction of components and their connections (NE);
4. the consistency check of the layout and circuit schematic diagram (LVS).
The usual order of validation is: DRC a ERC a NE a LVS. Map editing module and layout verification module nine days EDA system is interactive, can DRC, in the ZeniLE environment called ZeniVERI verification module ERC, NE online examination, the specific operation is: in ZLE, open the menu Verify-Layout Verfication form input, compiled DRC, ERC and NE to verify the command file. In
Row layout verification, and then through the show error form, we can see some DRC and ERC errors in the current layout. These errors can be displayed in text or in graphic editor. When the whole layout is finished, after checking the DRC and ERC correctly, we need to verify the consistency of the layout and the circuit diagram, and compare the network diagram of the circuit diagram with the netlist of the layout. LVS validation can be done either in the LVS Dialog window form or in the command line.
4. MCA0133 chip layout design
MCA0133 is a non-contact detector chip, the chip circuit principle diagram design, using 3um aluminum gate CMOS Wuxi Shanghua Microelectronics Manufacturing Co. Ltd. a well P process design rules, follow the layout, unit configuration and wiring requirements for full custom layout design in nine days in the EDA system, and DRC ERC, NE and VLS verification, figure 5 shows the layout of the chip, the chip area is 1.35mmx1.53mm.
The development of spinning process design and management system based on C++ technology is an advanced strategy, which ensures the security, stability, reliability and data confidentiality of the system. It reflects the latest technology trend and is suitable for the future technology development. In developing, in order to ensure data security of the system, the connection between database and each other should be controlled by module's program code, so as to avoid the failure of user's manual modification, which results in the failure of logical relation established by the system. As an important module of the spinning process design and management system, the development of the gear building module should be realized.
(1) providing an operable interface to display, record human data, and generate data tables
(2) automatically parsing the formula string for the user.
(3) the data structure container is used to save the disassembled gear specifications.
(4) combined calculation of gear matching.