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LCD Touch Screen Controller

LCD Touch Screen Controller

Dec 13, 2017

 LCD touch screen controller includes a data interface module, memory module (FSMC_Ctrl (SDRAM_Ctrl), liquid crystal display module (TFT_Ctrl) and a touch control module (TOUCH_Ctrl), the block diagram shown in figure 2.

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LCD touch screen controller working process: microprocessor (STM32F407) through the FSMC bus to send data to the FPGA, the FSMC_Ctrl module to receive data, the timing control module SDRAM_Ctrl write memory SDRAM, the timing control of TFT_Ctrl module from SDRAM to read data in real-time display. The TOUCH_Ctrl module drives the touch control chip ADS7843 and sends the collected coordinates to the FSMC_Ctrl module to wait for ARM to read it regularly.


1.  Data interaction module

The data exchange module is the key to realize bidirectional data transmission, FSMC bus including CS chip select signal and write signal WR, read operation signal RD, the address bus AB 25: 0 (multiplexing mode), data bus DB 15: 0 and an address / data multiplexing control signal NADV (using multiplexed address line). Among them, the chip select signal CS, read and write operations of WR signal RD signal usually effective at low power. When writing operation signal WR for low power, ARM sends the liquid crystal display address and data to DB bus, the latch address on the rising edge of NADV signal, and the corresponding data on the rising edge of WR signal, which is displayed on the LCD after SDRAM cache. When the read operation signal RD is low, FPGA sends the touch coordinates to the DB bus. ARM realizes the touch operation according to the coordinate value of the mapping address space register, and the FSMC bus working sequence diagram is shown in Figure 3.

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2. Liquid crystal display module

According to the display principle of liquid crystal screen, the signal controlled by this module mainly includes pixel clock signal, line / field synchronous signal and enable signal. According to the timing requirement of LCD display, the LCD control timing is designed by FPGA, and the control of line signal, frame signal and hidden signal is realized.

Among them, the frame scan time sequence is based on HSYNC as the reference clock, HSYNC is used as the line scanning signal, and VSYNC is a frame synchronization signal, and the low level is effective. Each frame is scanned, the effective area of the front end of the VSYNC signal is a frame blanking shoulder (VBPD + 1), there is a rear frame blanking front shoulder (VFPD + 1), the effective VSYNC signal before there is a high level (VSPW + 1), said frame synchronization pulse width signal. Among them, VBPD, VFPD, and VSPW are based on the reference clock HSYNC. Similarly, for every row of scanning signals, there is also a hidden back shoulder (HBPD + 1), a hidden front shoulder (HFPD + 1), a row synchronous signal pulse width (HSPW + 1), and a pixel clock VCLK as a unit. For different resolution LCD screens, the display timing is different from those of the front shoulder, the hidden shoulder and the signal pulse width. The display driver can switch the different LCD screens only by changing these parameters.

In order to make the LCD screen display driver for a variety of different resolution, within the FPGA Verilog hardware language with pre VCLK, VBPD, VFPD, VSPW, HBPD, HFPD, HSPW parameters of different LCD screen, using the FSMC bus address line 2 as the control parameters of a LCD screen. In application, we only need to change the address of control bit map register to realize the configuration of parameters, which is suitable for different LCD screens and improves the portability of controller. The time sequence diagram of the liquid crystal display is shown in Figure 4.

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3. Memory module

The memory module includes data preprocessing module, SDRAM controller and cache module, mainly to complete the input data storage and display data read. The memory module structure shown in figure 5.

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4. Data preprocessing module

The data preprocessing module mainly includes the integration and caching of data. Because the data transmission rate of FSMC bus is much lower than the working frequency of SDRAM, in order to solve the rate mismatch between them, data is cached before data is written to SDRAM to prevent data loss.

In order to ensure the correspondence between the display data and address, prevent display error, the address and data information displayed by splicing, splicing after the data is written to a buffer FIFO (first in first out, FIFO), the write operation to wait for SDRAM.


5. Cache module

The cache module includes two single random access memory (random access memory, RAM), whose main function is to achieve continuous output ping-pong operation data by two RAM, the ping-pong operation principle as shown in figure 6.

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In order to realize the continuous display of the output data, in the depth of two internal SDRAM back-end FPGA call for 2048, width 16 RAM, through the input data stream selection unit "and" output data stream selection unit "to switch regularly, after RAM cache the data stream continuously sent to the data flow processing unit" processing.

The data of each frame in the display process, in the first to two line signal before the arrival of synchronous signal during the pre reading of the data in the SDRAM, RAM1 and RAM2 to write data in advance, so that in first an enable signal comes can successfully read the RAM1 data display completed immediately from in the pre SDRAM reads the next line data into RAM1.

In the second DE signal enable regions, RAM2 is read and displayed, and the process is the same as RAM1. In turn, RAM1 and RAM2 are read and written alternately to complete the continuous output of data.


6. sdram controller

Because LCD display requires continuous data output and no data interruption during every enabling signal, so we need to set the read operation of SDRAM as the highest priority. In the whole SDRAM control, we must center on data read control.

SDRAM controller mainly controls the initialization, refresh, read and write operations of SDRAM, and SDRAM's read and write control is the core of this module. It is the key to improve data update rate and reduce the burden of ARM data processing.

Therefore, the design of SDRAM controller is mainly aimed at improving the data update rate and reducing the two aspects of the ARM data processing burden.


In order to improve the rate of data updating, the method of time - sharing reading and writing is adopted to make full use of the idle time provided by the data buffer. A counter is also set up during the reading operation of SDRAM. The maximum value of the counter is M (M is the row pixel of different liquid crystal), so that the effective data can be written RAM in order to read conveniently.

On the one hand, read burst read mode is used in the process of operation in SDRAM, each read 256 data set once again waiting for the next read, until a valid data read; on the other hand, according to the ping-pong operation set up a separate counter, the maximum value is Y / 2 (Y for different pixels LCD), each completed 1 ping-pong operation counter plus 1, accumulated to the maximum zero indicates that a data display is completed, SDRAM to wait until the next frame to display data.

In the two waiting interval control controller to recover SDRAM data bus, write operation of SDRAM, shorten the waiting time of SDRAM write operation, a write operation by burst write mode, each burst 1 writes 8 data, effectively alleviate the resulting data loss problem of FSCM high speed and can not input data when saving the bandwidth of SDRAM, improves the data update rate.

A fixed refresh operation time (N is adjusted according to the liquid crystal resolution) in the first N row period of each frame data, which ensures that all Bank in SDRAM can be refreshed in 64ms, so as to avoid conflict between refresh operation and read and write operation.


In order to improve the display update rate, reduce the burden of data processing of ARM liquid crystal, will be in accordance with the Bank memory address buffer space is divided into 4 layers, each layer has 2MB, SDRAM controller through multi SDRAM multi buffer operation to achieve the hardware accelerator design, its working principle as shown in Figure 7.

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The accelerator realizes customized logic control through customized instructions and look-up tables, and achieves various operations of FPGA on data, such as performing complex mathematical operation functions, transferring data from one place to another, and performing the same operation many times.

In the liquid crystal display process, on the one hand, SDRAM will be divided into 4 levels, Bank1 as the bottom, in turn Bank2, Bank3, Bank4, through the multi operation, can not change the underlying premise of the display, modify the buffer area through the first instruction address to update a region without data ARM to send data;

On the other hand, SDRAM is divided into 4 buffers. By sending customized instructions, we use look-up table to perform mathematical operations on different buffer area data, and realize transparent display and other functions.

Storing the data before display frame in Bank1, storing the frame data to be displayed in Bank2 and Bank3, displaying the end of the last frame data, displaying the next frame data directly through the instruction, ensuring the integrity of the display frame data and improving the visual effect of the LCD. Through multilayer and multi buffer operation, a part of data processing is allocated to FPGA for parallel processing to reduce the burden of ARM data processing. Compared with ARM's serial processing mode, it can improve data update rate.