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Matching Of CMOS Transistors

Matching Of CMOS Transistors

Jan 17, 2018

The matching of transistors has a high frequency of application in analog circuits, such as some differential pair circuits, which depend mainly on the matching of the gate to the source voltage. At the same time, it is like a current mirror, which mainly depends on the matching of the leakage current. The normally matched layout design can reduce the voltage deviation to + 5mv, making the leakage current with an error of 1%.

(1)A finger shaped figure with the same length.

The matching of transistors with different lengths and widths is very poor. Even the matching of transistors must require the same channel length. Do not attempt to match transistors of different lengths and widths. An instance of the layout is shown in Figure 2 (a) (b).

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(2)All transistors have to have the same direction and close to each other. This can effectively reduce the influence of the analog circuit due to the function of the process error. An instance of the layout is shown in Figure 3 (a) (b).

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(3)The layout rules that use the same center of gravity.

The matching transistor with medium or above accuracy requires the same center of gravity layout, usually by dividing large transistors into even finger transistors, and putting them in a crossed array. For example, in the amplifying circuit with the same differential pair, using the layout method of the transistor and the center of gravity to get the sensitive analog circuit layout, so that there is a precise output. The layout example is shown in Figure 4.

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(4)The fabrication of fictitious devices at the end of the array transistor can ensure the precision of the last transistor.

(5)Do not use a metal connection on a transistor that needs to be matched, so that it is possible to avoid noise and coupling effects, especially some sensitive devices. The layout example is shown in Figure 5.

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(6)The transistors that need to be matched are as far away from the power - consuming devices, switching transistors, and digital transistors, which will reduce the coupling effect.

(7)To connect the gate of a finger like transistor is to use a wire and do not use polysilicon. In moderately matched and accurately matched CMOS transistors, the effect of metal wires is much better than that of polysilicon. An instance of the layout is shown in Figure 6 (a) (b).

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(8)The use of CMOS transistors is better than the PMOS transistor because the NMOS transistor has a better flexibility.


 1.  Matching of resistance

The following rules are very important for the matching of resistance. Usually, the resistance process error can be reduced to 3% through them.

(1)Follow the three matching principles: the resistance should be placed in the same direction, the same type of device, and close to each other. These principles are very effective for reducing the impact of process errors on the function of the simulator.

(2)Use the same type, the same width, the length resistance, and the same distance. An instance of the layout is shown in Figure 7 (a) (b).

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(3)For high precision resistance, it is suggested that the width of the resistance is 5 times the minimum width of the process, which can effectively reduce the process error. The layout example is shown in Figure 8.

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(4)A fictitious resistance is placed at both ends of the resistance that needs to be matched, so as to ensure that the width and length of the matching resistance can be achieved accurately. The layout example is shown in Figure 9.

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(5)Avoid the use of short resistance, because short resistance is more easily affected by process errors. Moderately matched resistors should generally be larger than 5 square resistors. The exact matching resistance is generally less than 50um.

(6)Use the cross array resistance. If there is a large amount of resistance in the array, it is suggested that the resistance be placed into a multi-layer structure to form a two-dimensional array. The layout example is shown in Figure 10.

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(7)The matching resistance is far away from high-power devices, switching transistors, and digital transistors to reduce the effect of misfit.

(8)Do not use metal connections on the matched resistance, and avoid the effect of coupling and noise as much as possible. The layout example is shown in Figure 11.

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(9)For some resistance less than 20 ohms, the resistance will be obtained by using the metal layer, and the accurate resistance will be obtained.