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Research On Design Of Radiation Hardened Layout For Integrated Circuit In Si Technology

Research On Design Of Radiation Hardened Layout For Integrated Circuit In Si Technology

Jan 16, 2018

1.  Overview

 With the continuous deepening of human exploration of the universe, more and more electronic devices have been used in the field of aerospace. The existence of large amounts of high-energy protons, neutrons, alpha particles and heavy ions in the space environment will have an impact on semiconductor devices in the electronic devices, and then seriously threaten the reliability and life of spacecraft. Therefore, in order to meet the needs of expanding aerospace and enhance the reliability and stability of semiconductor devices in the radiation environment, the research on the radiation effects of semiconductor devices and the reinforcement of radiation effects have become the research focus in the field of space applications.


  At present, as the mainstream technology of semiconductor devices, the bulk silicon CMOS process has entered deep submicron and even less than 100nm. The application of the semiconductor integrated circuit made from this process will be influenced by the effect of the total dose effect and the effect of the single particle effect on the radiation. The influence of radiation effects on semiconductor integrated circuits is characterized by threshold voltage drift, current and dynamic current increase, and logic function errors. Therefore, ordinary devices and circuit design methods can no longer meet the needs of space and military applications, and special radiation hardened design technology is needed.


2.  Analysis of radiation effect

2.1  Effect of total dose effect on devices

2.11  Effect of total dose effect on the oxide layer of device gate

 Whether silicon gate or metal gate device, there is a 50~200nm SiO2 layer between the gate and substrate. Under the radiation condition, the accumulation of positive charges will happen at the SiO2/Si interface. Such a positive charge accumulation will lead to the drift of the threshold voltage of the device, which will eventually affect the performance of the device. The variation of threshold voltage corresponding to the number of captured cavitation introduced by radiation can be expressed as:

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Formula: BH is the fixed positive charge part of the cavitation body density captured after the oxide is captured. The parameter h1 is the distance from the Si/SiO2 interface to the oxide, and the hole captured at this distance can be electronically combined with the substrate penetrating into the gate. Only when the oxide thickness is less than 2 x h1 (6 nm), no significant hole capture can be observed.


Figure 1 shows the gradual drift of the I-V characteristic curve of the typical NMOS and PMOS tubes with the increase of the total radiation ionizing dose. The X axis in the diagram is the gate voltage VG, and the Y axis is the drain current ID. 0 is the I-V characteristic curve of the device before unirradiated; 1, 2, 3 and 4 indicate the I-V characteristic curve of the device under different irradiated doses. As the time increases, the total ionization dose increases, and the drift of threshold voltage increases. For the NMOS tube, when the positive voltage of the gate is larger than the threshold voltage, the transistor begins to pass. For PMOS transistors, the transistors are connected when the negative voltage of the gate is less than the threshold voltage. According to figure 1 (a), the threshold voltage drifts in the negative direction with the increase of the total ionization dose of the NMOS tube, which shows a decrease in the threshold voltage. The transistors that should be cut off should be turned on, and the transistors that have to be on need to stop at the end of the time. Similarly, according to figure 1 (b), the PMOS tube increases with the increase of the total ionization dose, and the threshold voltage shifts to the negative direction, showing an increase in the threshold voltage. The transistors that should be guided are turned off, and the transistors that have to cut off need to be inable when conducting. According to the formula (1), the threshold voltage drift of the NMOS tube and the PMOS tube is approximately proportional to the square of the thickness of the oxide layer of the gate oxide layer.


Fortunately, with the reduction of the critical size of the process, the thickness of the oxide layer of the device decreases, and the drift of the I-V characteristic of the device is reduced. After entering 0.18 micron m, the gate oxide thickness is lower than 12NM, and the threshold voltage drift caused by radiation is significantly reduced or even disappeared. The influence of the mechanism on the device can be ignored in circuit design.

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2.12  Leakage region leakage caused by total dose effect

  The self alignment process of NMOS tube, the polysilicon gate is deposited on the thin oxide layer, formed by the active region is not covered by the source / drain into polysilicon, the manufacturing process of the circuit of high concentration, but the presence of the polysilicon gate and gate oxide oxygen transition zone produced the edge parasitic transistor, the parasitic transistor very sensitive to the total dose effect. Under the radiation condition, the positive charge accumulated on the edge of the SiO2 field will cause the leakage of the edge parasitic transistor. With the increase of the radiation dose, the leakage current of the edge parasitic transistor also rises rapidly. When the leakage current increases to the open state current of the intrinsic transistor, the transistor will permanently open, resulting in device failure. Figure 2 (a) is a schematic diagram of the top surface of the leakage mechanism, and Figure 2 (b) is a schematic diagram of the leakage mechanism section.

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The field oxide layer is originally isolated between adjacent MOS tubes. However, due to the total dose effect, the electron hole pair will be ionized in the presence of oxygen, and the interface state accumulated by the hole on the SiO2 side of the Si/SiO2 system will make the field oxygen form downward and form an electronic leakage path. The leakage motor is shown in Figure 3. The leakage path formed by the inverse of the field oxygen can extend to the adjacent MOS tube source / leakage zone, which will increase the static leakage current of VDD to VSS.

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2.2  Effect of single particle flipping effect on devices

 The single particle flipping effect occurs in a sequential circuit containing the storage structure. We take the latch as an example to explain the mechanism of the single particle flip effect. Figure 4 is a simple latch structure. When the output node is subjected to a single particle incident to form a "funnel effect", a large amount of charge is generated, as shown in Figure 5. Under the action of the electric field, the charge generated by the ionization is drifting in the device, which ultimately affects the state of the latch.

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 When the stored data is "0", the NMOS tube is on the ground. At this point, the leakage end of the PMOS tube is in the reverse bias state with the P-N junction formed by the N well, and the direction of the built - up electric field is directed from the N well to the PMOS leak end. When the leak end of PMOS is incident by a single particle, many electron hole pairs are ionized. Under the action of the electric field, a large number of holes drift to the leaky end of the PMOS, and the electrons drift to the N trap. When the number of positive charges drifts to the PMOS leakage end of a certain magnitude, it will change the state of the original storage "0" and turn to the storage "1". The principle is shown in Figure 6 (a). Similarly, when the stored data is "1", the PMOS tube is on the power supply. At this time, the leakage end of the NMOS tube is in the reverse bias state with the P-N junction formed by the P- substrate, and the direction of the built - up electric field is directed from the leakage end of the NMOS tube to the P- substrate. When the leak end of the NMOS is incident by a single particle, many electron hole pairs are ionized. Under the action of the electric field, a large number of electrons drift to the leaky end of the NMOS, while the cavitation is drifting to the P- substrate. When the number of negative charge drifts to NMOS reaches a certain level, it will change the original storage state of "1" and change it to "0", which is shown in Figure 6 (b).

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 From the above analysis, it is not difficult to find that the single event upset effect is due to the existence of a reverse P-N junction in the CMOS circuit structure, and the drift of the electric charge is realized by the built-in electric field, which affects the original logic state.