1. the rational distribution of space through the overall situation
AX5318 is a CMOS calculator chip, including four operations, take root storage operation, overflow display, automatic power-off, can use 1.5V batteries, and can directly drive LCD. The customer needs to be compressed on the basis of the original product AX5315, because AX5315 uses 3V power supply, so it is necessary to increase the voltage doubling circuit in the original AX5315. Based on the original AX5315 layout analysis, can see a random logic block diagram of the A original position on the map in the upper right corner, but the input and output signals are most in the upper left corner of the map, and the domain size for this random logic block A, shape and to increase the voltage doubling circuit is very similar; at the same time, the original map under the direction of the connection is more complex, more clear about the direction of the connection, so it can be taken as the layout of Figure 1, the original random block logic A moved up with similar shape doubling circuit; and the random logic block A shaping processing to a thin strip, into the territory to void the compressed. This makes the connection of the original graph more reasonable, and it makes use of space effectively. According to this scheme, the area of the layout is reduced by 12.1%, and the target is 8% of the original requirement.
2. first find the power line and ground wire and then compress
Generally speaking, the work of compressing the layout is done by several people. After determining the layout plan, the whole layout is divided into several parts, and the final part is aggregated. If the power line and ground wire are not found in advance, all the connections are treated equally, and the performance of the chip will be affected. First, because the current flowing through the power line and the ground wire is large, it should be coarsely drawn than the general signal line. Secondly, the general signal line can be connected by POLY, while the power line and ground wire can only be connected by metal, and POLY connection is not allowed. If the changes are made in the summary, it is very difficult to use less space. Therefore, before compression, we should first confirm the power line and the ground line, and will not take more detours, and can achieve twice the result with half the effort.
3 . DRC inspection rules must be carefully written
The DRC rule is a rule that is used to check whether the layout of the layout data meets the requirements of the process. To write DRC rules is not only to meet the technological requirements, but also to take into account the mistakes that may be made in the drawing process. A good DRC rule can check all kinds of concealed errors in the publishing map design, and make the layout design reliable and reliable. DRC rules need to be noted.
1) make clear the exact meaning of every command in DRC rule file, especially for different tools, the same order of command may be different, and the number may also be different. For example, in DRACULAR, we need to check the spacing between POLY layers in the EXT. We only need one EXT command, such as Formula 1, while in DIVA, we need SEP and NOTCH two commands to achieve the same purpose, such as formula (2).
In form (2), SEP is used to check the spacing as shown in Figure 2, and NOTCH is used to check the spacing as shown in Figure 3. For Figure 4, it is possible to check the spacing between different layers of graphics (POLY and METAL) with only one SEP command. If you do not carefully understand the correct usage of each command, it is easy to make mistakes and lead to the serious consequences of the error of the layout. Compared with the two tools of DRACULAR and DIVA, DRACULA command has a wide range of commands, and commands are written simply and universality. It is recommended to use it as the preferred tool to write DRC rules.
2) the rules to meet the requirements of the process should be carefully written, and some mistakes that are easy to be made in the layout of the design, such as (all in the form of DIVA), should be considered.
In a word, it is not an easy thing to write a good DRC file. It needs to be very familiar with the process and the accumulation of experience.
4. LVL examination
Because the compression of the layout increases the voltage doubling circuit, so it can not simply check the layout of AX5315 with LVL. At the same time, because the chip contains ROM area, it can not draw schemas and do LVS inspection, so AX5318's verification problem is more difficult. After repeated discussions of various methods, finally using the following method, firstly, to add a voltage doubling circuit layout of LVS examination, to ensure the correct; then no data in the AX5315 domain, and then define some new connection layer and the connection hole, the input and output voltage doubling circuit connected to the to the right place in AX5315. This gives the reference layout for the LVL check. Because the original AX5315 layout is correct, and the voltage doubling circuit has been LVS check is correct, so if the error is only possible in multiple voltage circuit, the output port of entry on the line, the error rate has been greatly reduced; at the same time take different data handled by different people to the probability of such different designers make the same mistake will be less. The concrete realization method of this kind of verification idea is as follows:
Define the new layer:
The cutting layer used for LVL inspection, used to cut off the data that is not needed
The connection layer used for LVL inspection, used for interface connection
The LVL checks the pore layer for the connection between the LVL-ROUT layer and the AX5315 data, and defines the three layers of the connection (DRACULAR format) in the LVL rule file:
Through the LVL-CON connection LVL-ROUT and METAL, POLY, NDIFF, PDIFF layer is reflected in the layout, as shown in Figure 5