Study Of LVS Methodology For Layout Physical Verfication

Study Of LVS Methodology For Layout Physical Verfication

Jan 25, 2018

 Physical verification is the last link in the design of IC, and it is the interface between the design of the circuit and the process design. Therefore, it is particularly important for designers to verify the errors in the layout, and the layout verification system provided by Cadence has Dracula Diva. Diva is embedded in the main framework of Cadence, and it is more convenient to use, but the function is slightly inferior to that of Dracula. Dracula layout verification system independent, can be DRC (De -sign Rules Check), ERC (Elect rical Rules Check), LVS (Layout Versus Schematic), LPE (Layout Parameter Ex -tract ion) and a series of verification work, its operation speed, powerful function, can verify and extract a larger circuit.

1   LVS working process and principle

(1) The network table compiled with LOGLVS first needs to use LOGLVS to convert the network table of the schematic into a transistor level net table. L OGLVS can be converted to a variety of formats, such as Verilog, EDIF, TEGAS5, SICE, and so on. Since the first three logical network tables do not contain transistor level descriptions of basic logic units, it is necessary to provide a transistor level circuit description file CDL of basic logic units to generate the whole logic.

The transistor level net table LVSLOGIC. DAT of the circuit. In the process of conversion, L OGLVS compiles the logical nettable file, expands the module, and integrates the transistor level description of the basic logic unit with the logical network table. For transistor level net table SPICE, the process of conversion is relatively simple.


(2)Creating and compiling a regular file ( Rules file)

A rule file is a text file that contains Dracula commands created by users. These commands specify the verification operation used in the design, so the compilation of regular files is very important. The rule file consists mainly of three parts, such as the description block Description block, the layer definition block Input-layer block, the operation command block Operat ion block, and so on.

①  Description block

 This part defines what platform the Dracula runs on, and contains some information about the circuit that will be verified, such as execution mode, circuit module name, input / output file name and format, etc. When LVS is validated, the SCHEMATIC command is essential and is used to specify the transistor level net table file LVSLOGIC. DAT generated by the LOGLVS conversion. The following is an example of a description block:


       PRIMARY=TOP       ;To verify the name of the module

       PROGRAM-DIR=<path > ; Verifying the path of the tool

       SYSTEM = GDS2               ; Format data format

       INDI SK=<path>top. gds ; Layout data file

       RESOLUTION =0. 01MIC  ; Layout resolution

       PRINTFILE =1vs             ; Define the name of the printout file

       MODE=EXEC NO             ; Defining operation mode

       SCHEMATIC =L VSLOGIC ; Circuit network tables generated by LOGLVS

       TEXT-PRI- ONLY=YES    ; Use the tag of the top layer discovery as the node name


② Input-Layer block

 This part is used to link the number or name of the layout with the name of the Dracula layer, and at the same time, stipulate other information about Dracula required by the layer. When we use these layers in the operation command block, we can use the name of the layer. The following is an example of the layer definition block, and the specific definition of the layer described in the block is shown in Figure 2.


NW=1                       ; Definition of N well

PN=2                                            ; Defining active region

POLY=3 TEXT3 ATTACH POLY  ; Polycrystalline silicon layer

MET=4 TEXT4 ATTACH MET     ; Define the metal layer

NPLU=5                                        ; Define N+

PPLU=6                                        ; Define P+

CONT=8                                       ; Definition of contact holes

SUBSTR ATE =SUB 100               ; Define the substrate

CONNECT -LAY =PSUB NSUB NWELL PDIFF NDIFF POLYMET ; Define the contact layer and priority (from low to high)


③ Operation block

 This part is mainly based on the logical operation of the defined layer, such as AND, OR, NOR and so on to identify the devices. In addition, we define the operation to run and mark the errors that appear, which must include the LVSCHK command, which specifies Dracula to perform LVS verification operation, rather than other operations such as LPE.

  In this block, an "ELEMENT MOS" command is used to define an aluminum gate or a silicon gate MOS device. The command format is: ELEMENT MOS













=5  ; LVS Verification command


 In addition, NMOS, resistors, capacitors and other devices with PMOS definitions in this example is similar to the.

  After the rule file is created, it can be compiled with the PDRACULA preprocessing tool. First, check the rules of grammar in the document, through the rear of the rule files, and save the results for the executable file jxrun. com or jxsub. Com, the type]}la yer-a layer- B {[LA yer-c{layer-d} Type, which used to indicate the type of MOS devices, such as CMOS in the upper slide type [P] for [N], type of drop tube. Layer-A is the device layer. For the silicon gate MOS tube, the channel layer is usually defined by the overlapping of the polysilicon and the diffusion layer. La yer -b is a gate lead contact layer, to the silicon gate MOS tube, which is polysilicon. Layer-c source / drain contact layer on the silicon gate MOS, the definition of the layer can be removed in the diffusion layer of the channel region operation. La yer-d is used to define the substrate contact layer. The following examples of how to operate the layer to identify the PMOS tube are shown, as shown in Figure 3, as shown in the PMOS layout.


The executable file contains the command to submit the Dracula task.

 The libraries used during the validation operation should be located in the current run directory or by the path specified to the running directory. If the library is not located in the current run directory, a link from the library to the running directory is created by Pdracula and added to the executable file.

( 3 )  Execute LVS

Run the executable file for LVS validation.

  In the process of LVS operation, we first convert the data of the circuit diagram and the layout into an easy comparison circuit model, and then track the two circuit models with the input and output nodes as the starting nodes. The initial point of the initial corresponding node as the starting point for the LVS tracking operation can be provided by the designer. When the nodes in a layout are exactly the same as those of the conforming nodes in the schematic, they are used as a pair of initial corresponding node pairs. A qualified node can be a power node, a ground node, a top-level input / output node, or an internal node (depending on the network table format of schematic diagram). LVS selects all the power nodes, ground nodes, clock nodes, and at least one other type of node as the minimum set of initial corresponding nodes. As the program uses these initial corresponding nodes for tracking operations, the more initial corresponding nodes are provided, the more efficient the tracking is. However, LVS does not check whether the initial corresponding node pair is really matched. If the initial corresponding node pair has errors, it is used as a benchmark and tracking operation will be misled. Since manually adding tags to the layout database is more error prone, it is necessary to provide the minimum number of initial corresponding node pairs that are sufficient for effective inspection. So, it should be all the pins are used as the initial node corresponding to, in addition, also including the signal node, and many important module connected nodes or highly parallel circuit (such as bus) node, more important is to ensure that the same name tag on the territory of each node and logic principle diagram corresponding to this you can determine the initial node to correct. If Dracula does not find the initial corresponding node, it will find the automatic matching function for tracking. Dracula uses the heuristic method to start from the initial corresponding node pair, and gradually tracks the expanded layout net table and the principle graph net table. The first is the I /O circuit, and then tracks the paths that require the least backtracking. At the beginning, LVS thought that all the corresponding node pairs were matched. Whenever the matching object was found between the layout and the schematic diagram, and the matching condition was unique, it recognized the object as a matching node or module. When all nodes and modules are matched or all the points of disambiguation (the difference point, discrepancy point) are found, the LVS is stop tracking. That is to say, it is wrong to decide the bifurcation point positioning and key point to explain the mistake, but not the matching unit or module, due to a bifurcation point may cause the node or module does not match a series of instructions for the LVS bifurcation point, and node module reports with specific bifurcation point related matching or not. With it, therefore, does not match the number of nodes or the module can be different from the number of bifurcation point.

(4) Error report output

  After the LVS comparison, Dracula creates a report file that contains all the difference information. The report contains the corresponding node of information, schematics and layout of each matching and no matching device number, difference information list (including node name, and related information, and device) and circuit diagram and layout each other there is no correspondence between the name of the device list.

According to the hints of the error report, the steps to modify the layout are:

( a )Make the layout and the I/O pin of the circuit map one by one.

( b )To ensure that the number of devices is consistent with the layout of the circuit diagram, it is very important to find the location of the bifurcation points and make appropriate changes according to the difference information in the report.

( c )Update GDS II, compile rule files, and verify LVS;

( d )Repeat (b) and (c) operation until the layout is exactly the same as the circuit diagram.

  Following is a list of information difference error in the report example, the list of the circuit principle diagram of the information, the right for the layout information, were listed two points of difference, information about the first difference information for tracking nodes do not match those of the 4, second difference information for tracking the node 8 the result, according to the information, draw the connection diagram and layout as shown in Figure 4, through the analysis of the two different information describing the same mistake, just follow from different nodes, its purpose is to help the designers to easily find the key mistake, so in the analysis of errors note that the node is not listed in the report are wrong, but these nodes are associated with a specific bifurcation, the designer through the analysis of relevant node information will not be difficult to find a bifurcation point The.



 In the IC design process, using LVS Dracula verification tools, can quickly and accurately complete the consistency verification of layout and the principle diagram of the tool can be separated into two different representations of any design, and make a clear report for further analysis, completion of the layout changes in good designers, reduce the design process is repeated, and thus significantly reduces the design cost, improve the reliability of the design.